Scopus
Article
1
A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power
Wang J.S., Liu C.T., Hou Y.C.
IEEE Journal of Solid-State Circuits
2025
Article
2
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency
Wang J.S., Kuo Y.H.
Integration
2024, 97
Article
3
Clock Period-Jitter Measurement with Low-Noise Runtime Calibration for Chips in FinFET CMOS
Wang J.S., Chou P.Y.
IEEE Transactions on Circuits and Systems I: Regular Papers
2024, 71 (7) , 3157-3164
Conference Paper
4
In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection
Wang J.S., Miu Y.C., Wu C.H.
APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
2024 , 69-73
Conference Paper
5
A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing
Lin T.J., Li Z., Chen Y.C., Liu C.T., Chen T.F., Wang J.S.
2024 IEEE Hot Chips 36 Symposium, HCS 2024
2024
Conference Paper
6
Oriented IC Design Approach for Small-Volume, Performance-Demanded Edge-AI ASICs
Wang J.S., Chien C.S., Yeh C., Lin T.J., Liu C.T., Wu J.H.
Proceedings of the 2024 10th International Conference on Applied System Innovation, ICASI 2024
2024 , 389-391
Article
7
A 16 nm 140 TOPS/W 5 μj/Inference Keyword Spotting Engine Based on 1D-BCNN
Lin T.J., Ting Y.H., Hsu M.Z., Lin K.H., Huang C.M., Tsai F.C., Sheu S.S., Chang S.C., Yeh C., Wang J.S.
IEEE Transactions on Circuits and Systems II: Express Briefs
2023, 70 (12) , 4564-4568
Article
8
A low-power fast-switching write-and-standby shared assist circuit for low-voltage SRAMs
Wang J.S., Liu C.T., Liu Z.R., Wang S.Z., Kang J.J.
Electronics Letters
2022, 58 (7) , 262-264
Conference Paper
9
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients
Lin T.J., Liao C.Z., Hu Y.J., Hsu W.C., Wu Z.X., Wang S.Y., Huang C.M., Lai Y.H., Yeh C., Wang J.S.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2022, 2022-January , 7-8
Conference Paper
10
Low-Active-Energy and Low-Standby-Power Sub-Threshold ROM for IoT Edge Sensing Systems
Wang J.S., Liu C.T., Wang C.H.
2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
2020
學術著作
81
The Missing Charge-Sharing Fault in CMOS Domino Circuits
Ching-Hwa. Cheng, Wen-Ben Jone, Jinn-Shyan Wang and Shih-Chieh Chang
2000 Year and The Fifth Symposium on Computer and Communication Technology
2000 年
月
2000 Year and The Fifth Symposium on Computer and Communication Technology,pp.-
研討會論文
82
Low-speed testing of charge-sharing faults in CMOS Domino circuits
C.H. Cheng, J.S. Wang, S.C. Chang and W.B. Jone
in Proceedings of the 11th VLSI Design/CAD Symposium
2000 年
8 月
in Proceedings of the 11th VLSI Design/CAD Symposium,pp.393-396
研討會論文
83
Synthesis for charge sharing alleviation of Domino circuits2000.
Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shen-Da Li and J.-S. Wang
in Proceedings of the 11th VLSI Design/CAD Symposium
2000 年
8 月
in Proceedings of the 11th VLSI Design/CAD Symposium,pp.243-246
研討會論文
84
Energy-efficient cache architecture for embedded systems
Hung-Cheng, H. Y. Lee, Tien-Fu Chen and J.-S. Wang
in Proceedings of the 11th VLSI Design/CAD Symposium
2000 年
月
in Proceedings of the 11th VLSI Design/CAD Symposium,pp.137-140
研討會論文
85
A high-speed single-phase-clocked CMOS priority encoder
Jinn-Shyan Wang and Chun-Hsun Huang
in Proceedings of the 11th VLSI Design/CAD Symposium
2000 年
月
in Proceedings of the 11th VLSI Design/CAD Symposium,pp.121-124
研討會論文
86
A new high-speed and low-power NOR-type ROM for ASIC application
Jinn-Shyan Wang, Ching-Rong and Cheng-Hui Yang
in Proceedings of the 11th VLSI Design/CAD Symposium
2000 年
8 月
in Proceedings of the 11th VLSI Design/CAD Symposium,pp.125-128
研討會論文
87
Charge sharing fault analysis for CMOS Domino logic circuits
Jinn-Shyan Wang, C.H. Cheng, W.B. Jone and S.C. Chang
in Proceedings of the 11th VLSI Design/CAD Symposium
2000 年
8 月
in Proceedings of the 11th VLSI Design/CAD Symposium,pp.389-393
研討會論文
88
Design of a 3-V 300-MHz low-power 8-bI8-b pipelined multiplier using pulse-triggered TSPC flip-flops
Jinn-Shyan Wang, Po-Huei Yang and Duo Sheng
IEEE J. Solid-State Circuits
2000 年
4 月
IEEE J. Solid-State Circuits,Vol.35, No.4,pp.583-592
期刊論文
89
Low-power embedded SRAM with the current-mode write technique
Jinn-Shyan Wang, Wayne Tseng and Hung-Yu Li
IEEE J. Solid-State Circuits
2000 年
1 月
IEEE J. Solid-State Circuits,Vol.35, No.1,pp.119-124
期刊論文
90
A new high-speed/low-power dynamic CMOS logic and its application to the design of on AOI-type ROM
Ching-Rong Chang and Jinn-Shyan Wang
IEEE International Symposium on Circuits and Systems
1999 年
月
IEEE International Symposium on Circuits and Systems,pp.I254-I257
研討會論文