Scholar's profile
Chung, Ching Che
Chung, Ching Che
Professor
Department of Computer Science and Information Engineering
wildwolf@ccu.edu.tw
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Scopus Data (view scopus profile)

Publication Achievements 2002 - 2025
Publication Index
Documents
87
CITATIONS
1164
H-INDEX
15
FWCI
0.56
Co-authors
79
Last Sync Date: 2025-10-02

Google Scolar

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ORCID

0000-0003-1398-4320
Overview Research output
Research output per year
2002
2025
40
Article
46
Conference Paper
1
Editorial

Scopus

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1

Publication

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  • 1 A low-power convolutional neural network implemented in 40-nm CMOS technology for bearing fault diagnosis
    Yu-Pei Liang; Hui-Hsuan Chang; Ching-Che Chung
    International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) 2024 / 4
    Seminar Paper
  • 2 A binary weight convolutional neural network hardware accelerator for analysis faults of the CNC machinery on FPGA
    Ching-Che Chung; Yu-Pei Liang; Ya-Ching Chang; Chen-Ming Chang
    International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) 2023 / 4
    Seminar Paper
  • 3 Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery
    Ching-Che Chung; Yu-Pei Liang; Jo-Chen Huang
    IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW) 2023 / 7
    Seminar Paper
  • 4 A body channel communication transceiver with a 16x oversampling CDR and convolutional codes
    Ching-Che Chung;Yi-Ting Tsai
    International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) 2022 / 4
    Seminar Paper
  • 5 Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator
    Ching-Che Chung、Wei-Ting Chen、Ya-Ching Chang
    Indo-Taiwan 2nd International Conference on Computing, Analytics and Networks (Indo-Taiwan ICAN) 2020 / 2
    Seminar Paper
  • 6 An all-digital built-in self-test circuit for ADPLLs in 65nm CMOS technology
    Ching-Che Chung、Wei-Jung Chu、Yi-Ting Tsai
    29th VLSI Design/CAD Symposium (VLSI CAD) 2018 / 8
    Seminar Paper
  • 7 FPGA-based accelerator platform for K-means clustering algorithm
    Ching-Che Chung, Dai-Hua Lee and Yu-Hsin Wang
    Annual Conference on Engineering and Applied Science (ACEAT) 2017 / 11
    Seminar Paper
  • 8 A 0.52V/1.0V fast lock-in ADPLL for supporting dynamic voltage and frequency scaling
    Ching-Che Chung, Wei-Siang Su and Chi-Kuang Lo
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016 / 1
    Journal Article
  • 9 A 1 Mb/s – 40Mb/s human body channel communication transceiver,
    Ching-Che Chung, Chi-Tung Chang and Chih-Yu Lin
    International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) 2015 / 4
    Seminar Paper
  • 10 An all-digital on-chip voltage sensor for SoC design
    Ching-Che Chung, Mei-I Sun and Yi-Che Tsai
    26th VLSI Design/CAD Symposium (VLSI CAD) 2015 / 8
    Seminar Paper
1 2 3

Projects

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Teacher's name Research Units Year Project title Project position Commissioning unit Implementation period
Chung, Ching Che Department of Computer Science and Information Engineering 2024 教育部113年度先進製程IC設計及驗證環境建置計畫 SI 教育部 2024/07/01-2025/08/31
Chung, Ching Che Department of Computer Science and Information Engineering 2024 全自動AI智慧檢傷機器人 Co-PI 國家科學及技術委員會 2024/11/01-2025/09/30
Chung, Ching Che Department of Computer Science and Information Engineering 2024 113大專生計畫-開發無人機使用之神經網路硬體加速器用於實時野火偵測 PI 國科會 2024/07/01-2025/02/28
Chung, Ching Che Department of Computer Science and Information Engineering 2024 113年度晶片前瞻技術模組教材發展計畫 PI 教育部 2024/01/01-2025/03/31
Chung, Ching Che Department of Computer Science and Information Engineering 2023 112年度教學實踐-積體電路設計相關課程的遊戲化教學應用於遠距教學課程 PI 教育部 2023/08/01-2024/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2022 (陽明交大轉撥)111年度晶片前瞻技術模組教材發展計畫 PI 教育部 2022/10/01-2023/09/30
Chung, Ching Che Department of Computer Science and Information Engineering 2022 111大專生研究計畫-物理不可仿製功能研究及探討 PI 國科會 2022/07/01-2023/02/28
Chung, Ching Che Department of Computer Science and Information Engineering 2022 強化物聯網終端晶片工作環境監控與建立硬體安全系統之研究(II) PI 國科會 2022/08/01-2023/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2021 強化物聯網終端晶片工作環境監控與建立硬體安全系統之研究 PI 國科會 2021/08/01-2022/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2019 開發深度學習網路硬體加速器應用於工具機故障診斷及預防性維護(I) PI 國科會 2019/08/01-2020/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2018 適用於聲音情境分析之深層類神經網路硬體加速器設計及其應用之節能平台(I) PI 國科會 2018/08/01-2019/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2017 聲音情境分析、應用及其節能電路系統設計-子計畫四：適用於聲音情境分析與應用之節能平台及其深層類神經網路硬體加速器設計 PI 國科會 2017/08/01-2018/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2017 聲音情境分析、應用及其節能電路系統設計-總計畫暨子計畫二：適用於聲音情境分析之低功率高效能EMD演算及架構設計 Co-PI 國科會 2017/08/01-2018/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2016 1Mbps – 40Mbps 人體通道傳收器設計(3/3) PI 國科會 2016/08/01-2017/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2015 1Mbps – 40Mbps 人體通道傳收器設計(2/3) PI 國科會 2015/08/01-2017/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2015 可超寬調壓之智慧視覺處理晶片系統平台-子計畫四：針對 UDVS SoC 開發之全數位時脈產生器與晶片匯流排設計(3/3) PI 國科會 2015/08/01-2016/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2015 104年度智慧電子整合性人才培育計畫－主題領域模組課程發展計畫－時脈同步與責任週期校正／總計畫 PI 教育部 2015/03/01-2016/02/28
Chung, Ching Che Department of Computer Science and Information Engineering 2014 1Mbps – 40Mbps 人體通道傳收器設計(1/3) PI 國科會 2014/08/01-2017/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2014 可超寬調壓之智慧視覺處理晶片系統平台-總計畫暨子計畫三：適用於可超寬調壓晶片系統之抗變異記憶體與管線式電路設計(2/3) Co-PI 國科會 2014/08/01-2016/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2014 可超寬調壓之智慧視覺處理晶片系統平台-子計畫四：針對 UDVS SoC 開發之全數位時脈產生器與晶片匯流排設計(2/3) PI 國科會 2014/08/01-2016/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2014 智慧電子整合性人才培育--主題領域模組課程發展103年度計畫 PI 教育部 2014/03/01-2015/02/28
Chung, Ching Che Department of Computer Science and Information Engineering 2013 可超寬調壓之智慧視覺處理晶片系統平台-總計畫暨子計畫三：適用於可超寬調壓晶片系統之抗變異記憶體與管線式電路設計(1/3) Co-PI 國科會 2013/08/01-2016/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2013 可超寬調壓之智慧視覺處理晶片系統平台-子計畫四：針對 UDVS SoC 開發之全數位時脈產生器與晶片匯流排設計(1/3) PI 國科會 2013/08/01-2016/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2012 智慧電子整合性人才培育--高階應用處理器AP相關模組發展計畫--低功率系統時脈產生器模組課程計畫 PI 教育部 2012/12/01-2014/02/28
Chung, Ching Che Department of Computer Science and Information Engineering 2012 針對 A-UDVS iVP SoC 開發之抗變異全數位時脈產生器與晶片匯流排設計(I) PI 國科會 2012/08/01-2013/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2011 低功率儲存系統與高速傳輸界面電路設計 for iF2 Diary(I) PI 國科會 2011/08/01-2012/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2010 前瞻晶片系統設計人才培育先導型計畫--課程發展計畫--教材發展-系統晶片驗證平台與實作整合課程 Co-PI 教育部 2010/03/01-2010/12/31
Chung, Ching Che Department of Computer Science and Information Engineering 2010 (交大)Criti-core：超越多核心之高可靠度晶片系統平台技術開發-總計畫（2/2） Co-PI 國立交通大學 2010/08/01-2011/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2010 (交大)Criti-core：超越多核心之高可靠度晶片系統平台技術開發-總計畫（2/2） Co-PI 國科會 2010/08/01-2011/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2010 Criti-core：超越多核心之高可靠度晶片系統平台技術開發-總計畫(2/2) Co-PI 國科會 2010/08/01-2011/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2010 Criti-core：超越多核心之高可靠度晶片系統平台技術開發-子計畫四：Criti-Core之溫度感知與電源管理電路設計(2/2) PI 國科會 2010/08/01-2011/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2009 Criti-core：超越多核心之高可靠度晶片系統平台技術開發-總計畫(1/2) Co-PI 國科會 2009/08/01-2010/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2009 Criti-core：超越多核心之高可靠度晶片系統平台技術開發-子計畫四：Criti-Core之溫度感知與電源管理電路設計(1/2) PI 國科會 2009/08/01-2010/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2009 快速相位鎖定高頻率倍數全數位鎖相迴路設計與應用之研究(2/2) PI 國科會 2009/08/01-2010/07/31
Chung, Ching Che Department of Computer Science and Information Engineering 2008 快速相位鎖定高頻率倍數全數位鎖相迴路設計與應用之研究(1/2) PI 國科會 2008/11/01-2010/07/31

Patents

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Patents Apply Date Apply Number Patent Number Patent Country Inventor
全數位時脈校正電路及其方法 2012/01/20 101102418 I448081 R.O.C Ching-Che Chung
全數位時脈校正電路及其方法 2012/04/23 13/453,094 US 8,487,680 B1 U.S.A. Ching-Che Chung
具電磁干擾效應衰減之全數位位展頻時脈產生電路及其控制方法 2012/12/21 101149213 I505642 R.O.C Ching-Che Chung
具電磁干擾效應衰減之全數位位展頻時脈產生電路及其控制方法 2013/04/16 13/863,520 US 9,450,641 B2 U.S.A. Ching-Che Chung
Source：Chung Cheng Academic Achievements Information System