Scopus
Article
1
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency
Wang J.S., Kuo Y.H.
Integration
2024, 97
Article
2
Clock Period-Jitter Measurement with Low-Noise Runtime Calibration for Chips in FinFET CMOS
Wang J.S., Chou P.Y.
IEEE Transactions on Circuits and Systems I: Regular Papers
2024, 71 (7) , 3157-3164
Conference Paper
3
A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing
Lin T.J., Li Z., Chen Y.C., Liu C.T., Chen T.F., Wang J.S.
2024 IEEE Hot Chips 36 Symposium, HCS 2024
2024
Conference Paper
4
Oriented IC Design Approach for Small-Volume, Performance-Demanded Edge-AI ASICs
Wang J.S., Chien C.S., Yeh C., Lin T.J., Liu C.T., Wu J.H.
Proceedings of the 2024 10th International Conference on Applied System Innovation, ICASI 2024
2024 , 389-391
Article
5
A 16 nm 140 TOPS/W 5 μj/Inference Keyword Spotting Engine Based on 1D-BCNN
Lin T.J., Ting Y.H., Hsu M.Z., Lin K.H., Huang C.M., Tsai F.C., Sheu S.S., Chang S.C., Yeh C., Wang J.S.
IEEE Transactions on Circuits and Systems II: Express Briefs
2023, 70 (12) , 4564-4568
Article
6
A low-power fast-switching write-and-standby shared assist circuit for low-voltage SRAMs
Wang J.S., Liu C.T., Liu Z.R., Wang S.Z., Kang J.J.
Electronics Letters
2022, 58 (7) , 262-264
Conference Paper
7
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients
Lin T.J., Liao C.Z., Hu Y.J., Hsu W.C., Wu Z.X., Wang S.Y., Huang C.M., Lai Y.H., Yeh C., Wang J.S.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2022, 2022-January , 7-8
Conference Paper
8
Low-Active-Energy and Low-Standby-Power Sub-Threshold ROM for IoT Edge Sensing Systems
Wang J.S., Liu C.T., Wang C.H.
2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
2020
Conference Paper
9
A 0.21V 40nm NAND-ROM for IoT sensing systems with long standby periods
Wang J.S., Xue C.X., Liu C.T., Lin T.J.
Proceedings - IEEE International Symposium on Circuits and Systems
2020, 2020-October
Article
10
A Sub-mW On-Chip Period-Jitter Measurement Circuit Using Automatic Hidden Runtime Resolution Calibration
Chou P.Y., Liu Y.C., Lin T.J., Wang J., Wu K.C., Wang J.S.
IEEE Solid-State Circuits Letters
2020, 3 , 70-73
學術著作
1
A sub-mW on-chip period-jitter measurement circuit using automatic hidden run-time resolution calibration
Pei-Yuan Chou、Yen-Chen Liu、Tay-Jyi Lin、Jim Wang、KC Wu、Jinn-Shyan Wang
IEEE J. Solid-State Circuits Letter
2020 年
6 月
IEEE J. Solid-State Circuits Letter,Vol.3, No.,pp.70-73
期刊論文
2
An all-digital on-chip peak-to-peak jitter sensor with automatic resolution calibration for high PVT-variation resilience
Pei-Yuan Chou and Jinn-Shyan Wang
IEEE Transactions on Circuits and Systems I: Regular Papers
2019 年
3 月
IEEE Transactions on Circuits and Systems I: Regular Papers,Vol., No.,pp.-
期刊論文
3
Process/Voltage/Temperature-variation-aware design and comparative study of transition-detector-based error-detecting latches for timing-error resilient pipelined systems
Jinn-Shyan Wang and Shih-Nung Wei
IEEE Trans. on VLSI Systems
2017 年
10 月
IEEE Trans. on VLSI Systems,Vol.25, No.10,pp.2893-2906
期刊論文
4
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitivity-improved delay cells and adaptive-1P calibration for error reduction
Shang-Yi Lee, Pei-Yuan Chou and Jinn-Shyan Wang
IEEE ASP-DAC
2016 年
1 月
IEEE ASP-DAC,pp.262-265
研討會論文
5
Cross-matching caches: dynamic timing calibration and bit-level timing-failure-mask caches to reduce timing discrepancies with low voltage processors
Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang and Tien-Fu Chen
Integration, the VLSI Journal
2016 年
2 月
Integration, the VLSI Journal,Vol., No.54,pp.24-36
期刊論文
6
Sub-threshold SRAM bit-cell PNN for VDDmin and power reduction
Y.C. Chien, I.H. Chiang and J.S. Wang
Electronics Letters
2014 年
9 月
Electronics Letters,Vol.50, No.20,pp.1427-1429
期刊論文
7
A high-throughput and high-capacity IPv6 routing lookup system,
Yi-Mao Hsiao, Yuan-Sun Chu, Jeng-Farn Lee and Jinn-Shyan Wang
Computer Networks
2013 年
2 月
Computer Networks,Vol.57, issue 3, No.,pp.782-794, 2013-
期刊論文
8
Embedding Repeaters in Silicon Intellectual Properties for Cross-IP Interconnections
Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh and Shih-Chieh Chang
IEEE Trans. VLSI
2013 年
3 月
IEEE Trans. VLSI,Vol.21, No.3,pp.597-601, 2013
期刊論文
9
A 0.48V 0.57nJ/pixel video recording SoC in 65nm CMOS
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Gou, Tien-Fu Chen, Gene C.H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu and Jinn-Shyan Wang
in Proceedings of IEEE 2013 International Solid-State Circuits Conference, 9.3
2013 年
2 月
in Proceedings of IEEE 2013 International Solid-State Circuits Conference, 9.3,pp.158-159
研討會論文
10
Self super cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32-bit RISC core in 0.13m CMOS
Jian-Shiun Chen, Chingwei Yeh and Jinn-Shyan Wang
in Proceedings of IEEE 2013 International Solid-State Circuits Conference, 24.4,
2013 年
2 月
in Proceedings of IEEE 2013 International Solid-State Circuits Conference, 24.4,,pp.426-427
研討會論文